Implement Reliability, Availability and Serviceability (RAS) support for RISC-V architecture using RISC-V RERI specification and SBI SSE extension. This feature provides hardware error event handling and reporting capabilities conformant to ACPI platform error interfaces.

Key changes include:

SBI SSE Extension Support:

Add Supervisor Software Events mechanism for non-maskable event notification from SBI firmware
Implement context switching with firmware saving registers a6/a7
Add __sse_entry_task per_cpu array for reliable current task tracking during SSE event delivery
Allocate dedicated stacks for each event and CPU to support event preemption
Handle event completion with proper interrupt simulation for signal delivery to user tasks
RAS Framework Integration:

Integrate with existing GHES driver framework using highest priority SSE events for hardware error delivery
Register GHES entries with SSE layer using GHES notification vectors as SSE events
Add RISC-V specific processor type and ISA string entries
Add GHES SSE fixmap indices for physical address mapping
Enable build and configuration support for RAS
The implementation ensures reliable hardware error event processing and maintains system stability during error conditions. SSE events can be delivered at any time including during exception handling, with proper context preservation and signal delivery mechanisms.

Co-developed-by: Clément Léger cleger@rivosinc.com
Signed-off-by: Clément Léger cleger@rivosinc.com
Co-developed-by: Himanshu Chauhan hchauhan@ventanamicro.com
Signed-off-by: Himanshu Chauhan hchauhan@ventanamicro.com
Tested-by: lupeng lu.peng3@zte.com.cn
Signed-off-by: lupeng lu.peng3@zte.com.cn
Signed-off-by: liuqingtao liu.qingtao2@zte.com.cn