Bug 1513 - Intel: Backport SPR RAPL new layout for Psys
Summary: Intel: Backport SPR RAPL new layout for Psys
Status: RESOLVED FIXED
Alias: None
Product: ANCK 5.10 Dev
Classification: ANCK
Component: drivers (show other bugs) drivers
Version: unspecified
Hardware: x86_64 Linux
: P3-Medium S3-normal
Target Milestone: ---
Assignee: xunlei
QA Contact: shuming
URL:
Whiteboard:
Keywords:
Depends on:
Blocks:
 
Reported: 2022-06-28 11:35 UTC by jiayingbao
Modified: 2022-08-03 15:45 UTC (History)
1 user (show)

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Description jiayingbao intel_group 2022-06-28 11:35:42 UTC 
Description of problem:
On Sapphire Rapids, the layout of the Psys domain Power Limit Register
is different from from what it was before.
Enhance the code to support the new Psys PL register layout.

Version-Release number of selected component (if applicable):
5.17
Commit ID:
e3039d9b3144594ce773000700f1137d71b0fd31

How reproducible:


Steps to Reproduce:
1.
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Actual results:


Expected results:


Additional info:
Comment 1 jiayingbao intel_group 2022-08-03 15:45:03 UTC 
patch merged