Description of problem: Clear IOMMU page table entry C bit if IOMMU_PROT_MMIO is set in prot. IOMMU_PROT_MMIO indicates pfn is MMIO rather than normal RAM. It makes no sence to set SME bit on IOMMU page table entry if the phyical address is PFN rather than DRAM, it even causes device P2P access fail, as device can't recognize SME bit, only memory controller can hanle SME bit properly. Version-Release number of selected component (if applicable): How reproducible: 100% Steps to Reproduce: 1. Create a SEV/CSV VM with two GPU card passthrough to the VM. 2. One GPU accesses the other GPU's MMIO memory region. Actual results: It fails to access the other GPU MMIO memory. Expected results: Access other GPU's mmio memory successfully. Additional info:
The PR Link: https://gitee.com/anolis/cloud-kernel/pulls/5558