Bug 27061 - serial: Add driver for the LRW UART
Summary: serial: Add driver for the LRW UART
Status: NEW
Alias: None
Product: ANCK 6.6 Dev
Classification: ANCK
Component: drivers (show other bugs) drivers
Version: unspecified
Hardware: riscv Linux
: P3-Medium S3-normal
Target Milestone: ---
Assignee: GuixinLiu
QA Contact: shuming
URL:
Whiteboard:
Keywords: HwEnablement
Depends on:
Blocks:
 
Reported: 2025-11-13 16:31 UTC by liuqingtao
Modified: 2025-11-17 11:18 UTC (History)
3 users (show)

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Description liuqingtao 2025-11-13 16:31:00 UTC 
This commit introduces a serial driver for the LRW UART controller,

Key features implemented:
- Support for FIFO mode (16-byte depth)
- Baud rate configuration
- Standard asynchronous communication formats:
  * Data bits: 5, 6, 7, 8, 9 bits
  * Parity: odd, even, fixed, none
  * Stop bits: 1 or 2 bits
- Hardware flow control (RTS/CTS)
- Multiple interrupt reporting mechanisms

Signed-off-by: Wenhong Liu <liu.wenhong35@zte.com.cn>
Signed-off-by: Qingtao Liu <liu.qingtao2@zte.com.cn>
Comment 1 小龙 admin 2025-11-17 11:18:37 UTC 
The PR Link: https://gitee.com/anolis/cloud-kernel/pulls/6037